Simulation/evaluation environment for a VLIW processor architecture

An optimizing compiler, which generates tree instructions in a VLlW assembly language. A translator from VLlW assembly code into PowerPC@ assembly code which emulates the functionality of the VLlW processor for the specific VLlW program. The emulating code also includes instrumentation for collecting execution counts of VLIWs, profiling information, and generation of predecoded execution traces. A cycle timer, invoked by the emulating code on a VLIW-by-VLIW basis, which processes VLlW execution traces as they are generated. The environment supports the evaluation of alternatives and trade-offs among the VLlW architecture, its compiler, and processor implementations. Emphasis has been placed on providing fast turnaround time for the development of compilation algorithms and an efficient compilation-to-simulation cycle which allows analysis of architecture/compiler tradeoffs over complete execution runs of realistic workloads.